1. Technical Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to incremental Elmore delay calculation.
2. Related Art
A physical design system comprises the placement of standard cells and macro cells, as well as routing of the nets that electrically connect the cells. A physical synthesis system optimizes a placed and routed netlist to satisfy user-specified constraints. These constraints could encompass several requirements including delay, area, power consumption, design rules, etc. Different types of routing techniques are also used in different phases of the physical synthesis. For example, during initial phases of physical synthesis, a virtual router may be used to compromise some accuracy for computation speed. During the later stages of physical synthesis, typically detailed routing with metal layer assignment is used to enable design closure. A physical synthesis system is often tightly coupled with static timing analysis and layout parasitic extraction.
Wires contribute to the delay of the circuit in several forms. Some of these include wire delay, delay induced on gates because of wire capacitance, crosstalk wire delay, etc. A popular wire delay model that is used in physical synthesis systems is the Elmore delay model, which was described in Elmore, W. C., “The transient response of damped linear network with particular regard to wideband amplifiers,” J. Applied Physics, 19:55-63, 1948. Elmore delay is the first moment of the impulse response, and can be written as a closed form expression in terms of design parameters.
Some physical synthesis systems optimize a circuit by iteratively replacing a gate in the circuit design with other functionally equivalent gates from a library of gates. Each time the physical synthesis system replaces a gate with another gate, the wire delay in a net that is electrically connected to an input of the replaced gate can change because replacing a gate changes the input capacitance of the gate. However, computing the Elmore delay every time a gate is replaced is computationally expensive. Therefore, conventional physical synthesis systems either do not re-compute the wire delay or use approximate approaches to adjust the wire delay whenever a gate is replaced. Unfortunately, this causes the circuit optimization to output sub-optimal designs or to output designs that have too many timing violations.